Designing and building a 1-bit register – 8 bit register – Part 3 | register

คุณกำลังพยายามค้นหาเกี่ยวกับหัวข้อ register? Leather20 นำเสนอเนื้อหาทันทีในหัวข้อของ Designing and building a 1-bit register – 8 bit register – Part 3 ในโพสต์ด้านล่าง.

Designing and building a 1-bit register – 8 bit register – Part 3.

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Designing and building a 1-bit register - 8 bit register - Part 3
Designing and building a 1-bit register – 8 bit register – Part 3

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ดูความรู้เพิ่มเติมเกี่ยวกับDesigning and building a 1-bit register – 8 bit register – Part 3.

Before we build the 8-bit registers for our computer, let’s design and build a 1-bit register.

The 8-bit registers we’ll actually use in our 8-bit computer will be simplified. We’re going to take a big shortcut—using the 74LS173—described at the end of this video. But before we get to that, this video shows how we could build a 1-bit register using more basic components.

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You can get all the components used in this video from any online electronic components distributor for a few dollars. See for more.

Complete parts list (everything in this video):
– Clock circuit from
– 1x 74LS04 (Hex inverter)
– 1x 74LS08 (Quad AND gate)
– 1x 74LS32 (Quad OR gate)
– 1x 74LS74 (Dual D flip-flop)
– 1x LED
– 22 gauge wire
– 5 volt power source (e.g., a USB phone charger).

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ดูว่าผู้คนกำลังมองหาอะไรเพิ่มเติมเกี่ยวกับหัวข้อนี้Designing and building a 1-bit register – 8 bit register – Part 3.

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#Designing #building #1bit #register #bit #register #Part

Designing and building a 1-bit register – 8 bit register – Part 3.

42 thoughts on “Designing and building a 1-bit register – 8 bit register – Part 3 | register”

  1. Even using the same approach, you could cut down on the number of NOT gates by just having a "LOAD" line (as shown) as well as a "NOT LOAD" line. As long as the fan-out for the NOT gate is good enough (it likely is for CMOS chips).

    Reply
  2. Out of curiosity I ordered all the kits from your site and it doesn't have some of these chips like the 74LS04 and the 74LS74 are we not meant to follow along with this part?

    Reply
  3. This video series is amazing! I really appreciate how to provided all the details on how to build a one-bit register to explain the theory and then pulled back to use the 4-bit register chips.

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  4. I know this Is a four years old video, but couldn't he Just put the load and the clock in an and gate and use that as the enable for the d flip flop so that It only changes when the load Is High and the clock Is pulsing. (I'm not native english so idk of this sounded weird)

    Nvm someone already answered the question

    Reply
  5. I have a question, if I may – instead of the implementation of the LOAD signal (explained @4:22), consisting of an inverter, two AND gates and one OR gate,
    why can't we use one AND gate with its output connected to the CLOCK input of the D flip-flop, one of its inputs connected to the CLOCK signal, and the other to the LOAD signal?
    This way the flip-flop would be getting its CLOCK only when the LOAD signal is high (1), so it would read and store the data (Dn signal) on the rising edge of the CLOCK signal, but only when LOAD is high.

    Isn't this exactly what we want, but with just one gate of additional logic, instead of four?

    Reply
  6. if you're going to build a bus out of discrete logic gates, you may as well really commit and build the gates themselves. i imagine both the physical space required to build an entire computer out of transistors, as well as the sheer length of wire in the project, would be the main issues to overcome

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  7. let me explain the ques mentioned in the video" why there using another form of NOR gate to control EA and LD in this design of register".
    so first let me explain why NOR gate: for you can encode 4 chips like this, separately arrange them together as a register group.
    chip in this video may represent as number 0 chip, as you need to offer 00 to EA or LD data.
    the same reason for why this form of NOR gate, in fact, it is just for the chip number 0 you see a NOR gate.
    but for chip number 1 2 3, you got the different input control gate.

    Reply
  8. Why dont we use the tri state buffer for the input also? The load value can act as the enable of the tri state and the output of tri state buffer can act as input to the flipflop.

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  9. 4:24 you can replace all of the gates with NAND Gates, hook it up the same way (but connect the load signal to both the inputs of the NAND Gate taking the place of the inverter), and everything works the same. And as an added bonus, you get to save yourself a couple of chips, as now you only need one instead of three.

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  10. Hey! I’m using an 8-bit register chip (74ls273) instead of the two 4-bit flip flops (74ls173) to build a register. Since the octal bus transceiver (74ls245) has two sets of inputs/outputs (A 1-8 and B 1-8), and only one set can be enabled at a time, can’t I use just one 74ls245 to both control the input/output of the register from the bus?

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  11. Wouldn't it be a easier to use a D-Flip-Flop but with an AND gate added after the CLK input, where the second input is the ENABLE bit? Then the register would only read from the bus whenever both the CLK and ENABLE are on. It wouldn't need to read its own output on every clock pulse if ENABLE is off as it currently does.

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  12. I used to really throw myself off when I saw AND gates with inverted inputs (its JUST a NOR gate! :)) or same with an OR with inverted inputs (it's just a NAND gate) — maybe this will help someone out there when they see those in data sheets, etc. — it's an easier way when electrically design chips, etc. is partially why they may do that, another is it's just another way to draw that gate from the boolean algebra — so when you see these, just realize that's what's going on and also the data sheet will say if it's the input is active LOW or HIGH sometimes it's not and you'll see inverted inputs (the dots on the inputs, etc)

    Explanation below:
    If the STANDARD truth table output for an AND is 0001 and you invert the INPUTS, you will get 1000 (because the inputs 00 are now 11 and 11 in an AND gate is 1 (so 00 == 1) — conversely, if your inputs are 11 into an AND gate, inverted they become 00, (so 11 == 0…the inputs 01 and 10 just swap so nothing's changes (try it on a truth table) — Try it out with dual inverted input and to give you NOR and dual inverted NOR to give you an AND again…..same with OR to NAND and NAND to OR 😊😊

    TRUTH TABLE (Inverted input AND)
    [[Sorry it's not the cleanest, it's a comment box I'm typing in, lo]]
    A | B | AND |*NOT A* | NOT B | NOR |
    0 | 0 | 0 | 1 | 1 | 1 |
    0 | 1 | 0 | 1 | 0 | 0 |
    1 | 0 | 0 | 0 | 1 | 0 |
    1 | 1 | 1 | 0 | 0 | 0 |

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  13. I read your bio on your website and, honestly, I can empathize a lot with you. I, humbly and objectively, would also consider myself smart and curious; however, the educational system has never been a way for me to show my best and, to this day, I still don't fully understand why. Seeing your videos reinforces my idea that you don't have to get the best grades in order to be smart. Thank you for providing such interesting content!

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  14. Hallo there. @ around 16:20, we see that the gate E_bar (or E conjugate) enters the two AND gates with an INVERSION gate. I mean that both AND gates have E-bar inputs inverted. Is this some kind of engineering point? Thank you!

    Reply

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